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Programmable Analog Delay Line PADL is digitally controlled delay lines. The devices has a high linearity of time characteristics and temperature stability. Series Connection: Passive delay lines of the same impedance can can perform as programmable delays, logic control delays, pulse-width. Active delay lines are designed to match a particular logic family and are drop in devices. While some active delay lines also use passive components to achieve.

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Title, FPGA PUF using programmable delay lines. Publication Type, Conference Proceedings. Authors, Majzoobi, M., F. Koushanfar, and S. Devadas. with the “Delay line” and “output clock multiplexer” parameter values. The Delay Block module consists of 12 delay units with programmable unit delays. The DS and DS are bit programmable delay lines designed to provide the ability to perform in-circuit timing adjustments to digital timing.

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A variable length, digital delay line apparatus utilizing a set of progressively increasing delay devices in conjunction with a set of digitally selectable. MONOLITHIC QUAD 4-BIT. PROGRAMMABLE DELAY LINE. (SERIES 3D). FEATURES. • Four indep't programmable lines on a single chip. • All-silicon CMOS technology. The 8S is a high-performance LVDS programmable delay line. The delay can vary from ns to ns in 10ps steps. The 8S is characterized to.